A Hardware Implementation of the Advanced Encryption Standard using PyRTL

All electronic data is encrypted to uphold the privacy of information. With today’s communication networks being heavily loaded, implementing encryption on hardware is desirable for higher speeds. This work demonstrates a hardware implementation of the Advanced Encryption Standard (AES), a block encryption algorithm, for the first time using PyRTL (a Python-based register transfer language). The use of PyRTL, as opposed to traditional hardware description languages (HDL), allows for immediate hardware synthesis, resulting in an instantaneous model and the assurance of functioning hardware. AES-128, implemented using the recursive and introspective features of PyRTL, is shown to be secure, and more concise than designs done in Verilog and VHDL. In addition, a functional mathematical analysis is used to ensure the absence of unattended gate-level information flows or security leaks.